In linear image sensors, signal charges generated in a plurality of light receiving elements arranged in a one-dimensional array are read out by one CCD. Recently, needs for higher resolution have increased and the number of light receiving elements has increased. However, as the number of light receiving elements increases, the number of stages of CCDs increases, resulting in a deterioration in the overall transfer efficiency, the data rate, and the like. In order to solve these problems, a solid-state imaging device shown in FIG. 10, in which light receiving elements are divided in the middle and signal charges are read out by two CCDs arranged serially has been proposed.
In FIG. 10, a plurality of photodiodes (light receiving elements) 4 constituting a light-to-electricity conversion part are arranged in a line on a semiconductor substrate 3, and two CCDs 5 are arranged parallel to the photodiode array. Respective photodiodes 4 are connected to the charge transfer part of the CCD 5 via corresponding transfer gates 6 and signal charges stored in the photodiodes 4 are transferred to the CCD 5 by the ON operation of the transfer gates 6. In addition, output amplifiers 7 are provided at the ends of the CCDs 5 and signal charges transferred through the CCDs 5 are amplified in the output amplifiers 7 and output from the solid-state imaging element 1. A charge input means 2 is provided between the initial stages of the CCDs 5, whereby charges, other than the charges from the photodiodes, are injected into the CCDs 5 from outside. This charge input means 2 electrically supplies charges to the CCDs 5 at the a time other than during the imaging mode thereby to check and calibrate the CCDs 5 and the output amplifiers 7 or to test the respective transfer electrodes constituting the CCD 5 .
FIG. 11 is a plan view showing the structure of the charge input means 2 in detail. In FIG. 11, reference numeral 10 designates a charge input terminal. Charge input controlling gates 8 and 9, which control the quantity of charges input from the charge input terminal 10, are provided at both sides of the charge input terminal 10. Reference numerals 11 and 12 designate transfer electrodes of the CCD 5.
Operation in the charge input mode will be described.
FIG. 12(a) is a diagram schematically showing a cross-section taken along a line C--C' of FIG. 11 and the corresponding potentials at times t.sub.1 to t.sub.4 in the charge input mode. FIG. 12(b) schematically shows waveforms of signals that are applied to the respective terminals.
Clock pulses I, .phi.1, and .phi.2 are applied to the charge input terminal 10, and signal input terminals of the transfer electrodes 11 and 12, respectively, and dc voltages V.sub.GIL and V.sub.GIH are applied to the signal input terminals of the charge input controlling gates 8 and 9, respectively.
First, at time t.sub.1, the charge input terminal 10 and the transfer electrode 12 are at "H" level while the transfer electrode 11 is at "L" level.
At time t.sub.2, the input signal I of the charge input terminal 10 becomes "L" level and charges are transferred from the charge input terminal 10 to the potential well beneath the input controlling gates 8 and 9. At time t.sub.3, the charge input terminal 10 again becomes "H" level and the input charges Q.sub.0 are stored in the potential well beneath the input controlling gate 9.
At time t.sub.4, .phi.1 is at "H" level while .phi.2 is at "L" level. The transfer electrode 11 becomes "H" level and the transfer electrode 12 becomes "L" level, whereby measured charges Q.sub.0 are transferred to the potential well beneath the CCD transfer electrode 11.
Next, operation in the imaging mode will be described.
FIG. 13(a) is a diagram schematically showing a cross-section taken along a line C--C' of FIG. 11 and the potential at times t.sub.1 to t.sub.3 in the imaging mode. FIG. 13(b) schematically shows waveforms of signals applied to the respective terminals.
Clock pulses .phi.1 and .phi.2 are applied to the signal input terminals of the transfer electrodes 11 and 12, respectively, and dc voltages V.sub.GIL and V.sub.GIH are applied to the signal input terminals of the charge input controlling gates 8 and 9, respectively.
Between times t.sub.1 and t.sub.2, the transfer gate (TG) 6 is opened and the signal charges Q.sub.1 and Q.sub.2 detected respectively in the light receiving elements 4-1 and 4-2 are transferred to the potential wells beneath the corresponding transfer electrodes 11.
At time t.sub.3, the signal .phi.1 of the transfer electrode 11 is set to "H" level and the signal .phi.2 of the transfer electrode 12 is set to "L" level, whereby the signal charges Q.sub.1 and Q.sub.2 are transferred to the potential wells beneath the transfer electrodes 12 at the next stage. Thereafter, by repeating this operation, the signal charges are synchronized with the clock pulses and successively transferred.
Since the charge input part 2 of the prior art linear image sensor is constituted as described above, the pitch of the light receiving elements 4 in the charge transfer part 2 is unfavorably larger than that at another region.
More specifically, in a case where the width of the transfer electrodes 11 and 12 is 8 microns and the interval between the adjacent light receiving elements 4-1 and 4-2 (in FIG. 11, l1) is 16 microns, the interval between the light receiving elements 4-1 (in FIG. 11, l2) is required to be 31 microns when the width of the charge input terminal is 4 microns and the widths of the charge input controlling gates 8 and 9 are 3 microns and 4 microns, respectively.
When the spacing of the charge input part 2 is large and the array pitch of the light receiving element 4 corresponding to this part is large, resolution is significantly lowered at the charge input part 2, so that a uniform resolution over the chip cannot be obtained.